1. Field of the Invention
This invention relates to a complementary logic circuit constituting a sequence circuit comprised of a delay circuit using a group of D (delay) type flip-flops and a combination circuit.
2. Description of the Prior Art
As a LSI (Large Scale Integrated) circuit for digital processing, complementary logic circuits of the CMOS (Complementary Symmetry MOS) structure, etc. have been conventionally known.
Generally, a sequence circuit is widely known as a logic circuit of which output is not determined by an input, but depends upon a past record or history of an input. Such sequence circuit is comprised, as shown in FIG. 1, for example, of a delay circuit 41 using a group of D (delay) type flip-flops adapted for delaying input data by one clock to output the delayed data, and a combination circuit 42 for determining a subsequent output from all or a portion of that output and an input.
More particularly, a D (delay) type flip-flop (hereinafter referred to as a D flip-flop) is comprised, as shown in FIG. 2, for example, of two sets of cascade-connected latch circuits, i.e., a master latch 43 and a slave latch 44. These master and slave latches 43 and 44 are respectively supplied with clocks .phi..sub.1, .phi..sub.2 opposite to each other in phase as an enable input. When the enable inputs are at high level, these latches are brought into a data through condition where input data directly outputted, while when they are at low level, those latches carry out a latch operation. Thus, it appears that the D flip-flop carries out an edge trigger operation as a whole.
Further, as a latch circuit, there have been conventionally known a static latch comprised of two analog switches 45, 46 and two inverters 47, 48 as shown in FIG. 3, and a dynamic latch comprised of a single analog switch 49 and a single inverter 50 as shown in FIG. 4.
Meanwhile, in a CMOS-LSI, the analog switch is comprised of two transistors, and the inverter is also comprised of two transistors. Accordingly, the static latch is comprised of eight transistors, and the dynamic latch is comprised of four transistors. Since the D flip-flop is constituted with two sets of latch circuits, it has 16 transistors in the case of the static type, and has 8 transistors in the case of the dynamic type.
For this reason, the occupation area of the D flip-flop of the dynamic type can be reduced to one half of that of the D flip-flop of the static type. Moreover, the static latch may involve an unnecessary power consumption due to the fact that the input sampling analog switch and the output holding analog switch are turned ON at the same time momentarily. However, the D flip-flop of the dynamic type has not such unnecessary power consumption because only one sample-hold analog switch exists. As a result, the quantity of power consumption can be reduced to a value less than one half of that of the static latch.
However, in the case of the dynamic latch, since data is held only by the gate capacity of two P-channel and N-channel MOS transistors constituting an inverter, it is possible to hold data only for a short time. For this reason, when the enable signal is stopped at low level, the gate voltage becomes unstable, and when it becomes an intermediate level between low level and high level, two P-channel and N-channel MOS transistors constituting inverter are both turned ON at the same time. Thus, an extraordinary large punch-through current will flow from the power supply toward the ground. Accordingly, such D flip-flop of the dynamic type is not suitable for a circuit required to be operated and stopped, so it could be used only in a circuit operative at all times.
For this reason, in a complementary logic circuit constituting a sequence circuit used in a manner switched between ON state and OFF state, it is impossible to allow a group of D flip-flops of the delay circuit to be of the dynamic type, so a group of D flip-flops of the static type having large occupation area and power consumption was adopted for the delay circuit.